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ics9ds400 idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 four output differential buffer for pcie gen 2 with spread advance information 1 general description output features the 9ds400 is pin compatible to the 9db403, but adds the ability to inject spread spectrum onto the incoming differential clock, while maintaining good phase noise. ? 4 - 0.7v current-mode differential output pairs. ? supports spread injection mode and fanout mode. ? tw o pin selectab le do wn spread amounts: 0.5% and 0.25%. ? 50-110 mhz operation in pll mode ? 50-400 mhz operation in bypass mode functional block diagram ke y specifications ? output cycle-cycle jitter < 50ps ? output to output skew <50ps ? phase jitter: pcie gen1 < 86ps peak to peak ? phase jitter: pcie gen2 < 3.0/3.1ps rms features/benefits? bypass mode ? supports undriven differential outputs in pd# andsrc_stop# modes for power management. recommended application db400 where spread spectrum needs to be added to theincoming clock. stop logic src_in src_in# dif(6,5,2,1)) control logic bypass#_sscg sdata sclk pd spread generating pll 4 iref oe(6,1)# 2 dif_stop spread_en m u x polarities shown assuming that oe_inv = 1
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 2 advance information pin configuration po wer gr oups vdd 1 28 vdda src_in 2 27 gnda src_in# 3 26 iref gnd 4 25 oe_inv vdd 5 24 vdd dif_1 6 23 dif_6 dif_1# 7 22 dif_6# oe_1 8 21 oe_6 dif_2 9 20 dif_5 dif_2# 10 19 dif_5# vdd 11 18 vdd bypass#_sscg 12 17 spread_en sclk 13 16 dif_stop# sdata 14 15 pd# oe_inv = 0 ics9ds400 vdd 1 28 vdda src_in 2 27 gnda src_in# 3 26 iref gnd 4 25 oe_inv vdd 5 24 vdd dif_1 6 23 dif_6 dif_1# 7 22 dif_6# oe1# 8 21 oe6# dif_2 9 20 dif_5 dif_2# 10 19 dif_5# vdd 11 18 vdd bypass#_sscg 12 17 spread_en sclk 13 16 dif_stop sdata 14 15 pd oe_inv = 1 ics9ds400 see pin descr iption t ab le f or pins w/inter nal pull up or pull do wn see pin descr iption t ab le f or pins w/inter nal pull up or pull do wn vdd gnd 1 4 src_in/src_in# 5,11,18, 24 4 dif(1,2,5,6) n/a 27 iref 28 27 analog vdd & gnd for pll core pin number description
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 3 advance information pin description f or oe_inv = 0 pin # pin name pin type description internal pull up or pull down? 1 vdd pwr power supply, nominal 3.3v n/a 2 src_in in 0.7 v differential src true input n/a 3 src_in# in 0.7 v differential src complementary inpu t n/a 4 gnd pwr ground pin. n/a 5 vdd pwr power supply, nominal 3.3v n/a 6 dif_1 out 0.7v differential true clock output n/a 7 dif_1# out 0.7v differential complementary clock out put n/a 8 oe_1 in active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs pull up 9 dif_2 out 0.7v differential true clock output n/a 10 dif_2# out 0.7v differential complementary clock ou tput n/a 11 vdd pwr power supply, nominal 3.3v n/a 12 bypass#_sscg in input to select bypass(fan-out) or sscg (pll) mode 0 = bypass mode, 1= sscg mode pull up 13 sclk in clock pin of smbus circuitry, 5v tolerant. n/a 14 sdata i/o data pin for smbus circuitry, 3.3v tolera nt. n/a 15 pd# in asynchronous active low input pin used to power dow n the device. the internal clocks are disabled and the vco and the cr ystal osc. (if any) are stopped. pull up 16 dif_stop# in active low input to stop differential output clocks. pull up 17 spread_en in asynchronous, active high input to ena ble spread spectrum functionality. pull up 18 vdd pwr power supply, nominal 3.3v n/a 19 dif_5# out 0.7v differential complementary clock ou tput n/a 20 dif_5 out 0.7v differential true clock output n/a 21 oe_6 in active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs pull up 22 dif_6# out 0.7v differential complementary clock ou tput n/a 23 dif_6 out 0.7v differential true clock output n/a 24 vdd pwr power supply, nominal 3.3v n/a 25 oe_inv in this latched input selects the polarity of the oe p ins. 0 = oe pins active high, 1 = oe pins active low (oe #) n/a 26 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is t he standard value. n/a 27 gnda pwr ground pin for the pll core. n/a 28 vdda pwr 3.3v power for the pll core. n/a
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 4 advance information pin description f or oe_inv = 1 pin # pin name pin type description internal pull up or pull down? 1 vdd pwr power supply, nominal 3.3v n/a 2 src_in in 0.7 v differential src true input n/a 3 src_in# in 0.7 v differential src complementary inpu t n/a 4 gnd pwr ground pin. n/a 5 vdd pwr power supply, nominal 3.3v n/a 6 dif_1 out 0.7v differential true clock output n/a 7 dif_1# out 0.7v differential complementary clock out put n/a 8 oe1# in active low input for enabling dif pair 1. 1 = tri-state outputs, 0 = enable outputs pull up 9 dif_2 out 0.7v differential true clock output n/a 10 dif_2# out 0.7v differential complementary clock ou tput n/a 11 vdd pwr power supply, nominal 3.3v n/a 12 bypass#_ss cg in input to select bypass(fan-out) or sscg (pll) mode 0 = bypass mode, 1= sscg mode pull up 13 sclk in clock pin of smbus circuitry, 5v tolerant. n/a 14 sdata i/o data pin for smbus circuitry, 3.3v tolera nt. n/a 15 pd in asynchronous active high input pin used to power do wn the device. the internal clocks are disabled and the vco is stopped . pull up 16 dif_stop in active high input to stop differential output clocks. pull up 17 spread_en in asynchronous, active high input to ena ble spread spectrum functionality. pull up 18 vdd pwr power supply, nominal 3.3v n/a 19 dif_5# out 0.7v differential complementary clock ou tput n/a 20 dif_5 out 0.7v differential true clock output n/a 21 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs pull up 22 dif_6# out 0.7v differential complementary clock ou tput n/a 23 dif_6 out 0.7v differential true clock output n/a 24 vdd pwr power supply, nominal 3.3v n/a 25 oe_inv in this latched input selects the polarity of the oe p ins. 0 = oe pins active high, 1 = oe pins active low (oe #) n/a 26 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohm s is the standard value. n/a 27 gnda pwr ground pin for the pll core. n/a 28 vdda pwr 3.3v power for the pll core. n/a
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 5 advance information absolute max symbol parameter min max units vdd 3.3v supply voltage 4.6 v v il input low voltage gnd-0.5 v v ih input high voltage v dd +0.5v v ts storage temperature -65 150 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v electrical characteristics - input/supply/common ou tput parameters t a =over the specified operating range; v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% gnd - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 operating supply current i dd3.3op full active, c l = full load; 125 ma 1 all diff pairs driven 30 ma 1 all differential pairs tri-stated 6 ma 1 f ipll pcie mode (bypass#/pll= 1) 90 100.00 110 mhz 1 f ibypass bypass mode ((bypass#/pll= 0) 33 400 mhz 1 pin inductance l pin 7 nh 1 c in logic inputs, except src_in 1.5 5 pf 1 c insrc_in src_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1 ms 1,2 ss modulation frequency f mod assuming 100 mhz input (triangular modulation) 30 32.000 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of pd# and src_stop# 5 ns 1 trise t r rise time of pd# and src_stop# 5 ns 2 smbus voltage v max maximum input voltage 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol i pullup 4 ma 1 sclk/sdata clock/data rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 see timing diagrams for timing requirements. input low current powerdown current capacitance 5 the differential input clock must be running for th e smbus to be active input frequency 4 src_in input i dd3.3pd 3 time from deassertion until outputs are >200 mv
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 6 advance information electrical characteristics - differential clock inp ut parameters ta =over the specified operating range; vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentiall y 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing min centered arou nd differential zero
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 7 advance information electrical characteristics - dif 0.7v current mode differential pair ta =over the specified operating range; vdd = 3.3 v +/-5%; c l =2pf, r s =33 , r p =49.9 , r ref =475 parameter symbol conditions min typ max units notes current source output impedance zo 1 3000 1 voltage high vhigh 660 850 1,2 voltage low vlow -150 150 1,2 max voltage vovs 1150 1 min voltage vuds -300 1 crossing voltage (abs) vcross(ab s) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossin g over all edges 140 mv 1 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 t pdbyp bypass mode, v t = 50% 2500 4500 ps 1 t pdpll pll mode v t = 50%, spread off -250 250 ps 1 skew, output to output t sk3 v t = 50% 50 ps 1 pll mode 50 ps 1,3 additive jitter in bypass mode 50 ps 1,3 pcie gen1 phase jitter (additive in bypass mode) 10 ps (pk2pk) 1,4,5 pcie gen 2 low band phase jitter (additive in bypass mode) 0.1 ps (rms) 1,4,5 pcie gen 2 high band phase jitter (additive in bypass mode) 0.5 ps (rms) 1,4,5 pcie gen 1 phase jitter 86 ps (pk2pk) 1,4,5 pcie gen 2 low band phase jitter 3 ps (rms) 1,4,5 pcie gen 2 high band phase jitter 3.1 ps (rms) 1,4,5 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . 3 measured from differential waveform 4 see http://www.pcisig.com for complete specs 5 device driven by 932s421c or equivalent. statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv skew, input to output jitter, cycle to cycle t jcyc-cyc jitter, phase t jphasebyp t jphasepll
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 8 advance information clock periods differential outputs with spread spec trum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.176 30 ns 1,2,3 dif 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2,4 dif 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2,4 dif 200 4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2,4 dif 266 3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2,4 dif 333 2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2,4 dif 400 2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2,4 clock periods differential outputs with spread spec trum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3 dif 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2,4 dif 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2,4 dif 200 4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2,4 dif 266 3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2,4 dif 333 2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2,4 dif 400 2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2,4 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, pll or bypass mode 4 driven by cpu output of ck410b/ck505 main clock, bypass mode only 2 all long term accuracy specifications are guarante ed with the assumption that the input clock complie s with ck409/ck410b/ck505 accuracy requirements. the 9ds4 00/800 itself does not contribute to ppm error. notes notes definition measurement window units symbol definition units signal name signal name measurement window symbol
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 9 advance information common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 10 advance information vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 11 advance information general smbus serial interface information for the ics9ds400 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address d8 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics cloc k will ac kno wledg e each b yte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the write address d8 (h) ? ics clock will acknowledge ? controller (host) sends the begining bytelocation = n ? ics cloc k will ac kno wledg e ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d9 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controllor (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d8 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d9 (h) index block read operation slave address d8 (h) beginning byte = n ack ack
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 12 advance information smbus table: frequency select register, read/write address ( d8/d9 ) pin # name control function type 0 1 default bit 7 pd_mode pd# drive mode rw driven hi-z 0 bit 6 stop_mode src_stop# drive mode rw driven hi-z 0 bit 5 0 bit 4 spread_amt(1) spread % msb rw latch bit 3 spread_amt(0) spread % lsb rw 1 bit 2 spread_en turns on spread rw ss off ss on latch bit 1 bypass# bypass#_sscg rw fan-out sscg latch bit 0 byte0 control selects control source of byte 0 rw smb us input pins 1 smbus table: output control register pin # name control function type 0 1 default bit 7 reserved reserved rw 1 bit 6 dif_6 output enable rw disable enable 1 bit 5 dif_5 output enable rw disable enable 1 bit 4 reserved reserved rw 1 bit 3 reserved reserved rw 1 bit 2 dif_2 output enable rw disable enable 1 bit 1 dif_1 output enable rw disable enable 1 bit 0 reserved reserved rw 1 note: the smbus output enable bit must be '1' and the res pective oe pin must be active for the output to run ! smbus table: oe pin control register pin # name control function type 0 1 default bit 7 reserved reserved rw 0 bit 6 dif_6 dif_6 stoppable with oe6 rw free-run stoppable 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 dif_1 dif_1 stoppable with oe1 rw free-run stoppable 0 bit 0 reserved reserved rw 0 smbus table: reserved register pin # name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x reserved reserved reserved reserved reserved reserved reserved - - reserved 6,7 - byte 3 - - - 9,10 - byte 2 - - 6,7 22,23 22,23 19,20 byte 1 - reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved byte 0 - - - reserved 1 00 = -0.125% 01 = -0.25% 10 = -0.375% 11 = -0.50% - 28 22 - notes: pins 1, 22 and 28 are latched into byte 0 on the first power up of the device. bits [4:1] will not reflect changes in these pin states after power up, even th ough the pins are controlling the function of the p art. setting byte 0 bit 0 to 0 allows the smbus to write bits [4 :1] and transfers control of the functions from the pins to smbus. once byte 0 bit 0 is set to 0, the pins no longer i mpact byte 0, bits [4:1] or the device function.
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 13 advance information smbus table: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function type 0 1 default bit 7 r x bit 6 r x bit 5 r 0 bit 4 r 0 bit 3 r 0 bit 2 r 0 bit 1 r 0 bit 0 r 0 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 device id 1 device id 6 device id 7 (msb) device id is 80 hex for 9ds800 and 40 hex for 9ds400 device id 5 device id 4 device id 3 device id 0 device id 2 byte 6 - writing to this register configures how many bytes will be read back. - - - - - - - byte 5 - - - - - - - - - vendor id - - - - revision id - - - byte 4
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 14 advance information the pd# pin cleanly shuts off all cloc ks and places the de vice into a po w er sa ving mode . pd# m ust be asser ted bef ore shutting off the input cloc k or po w er to insure an order ly shutdo wn. pd is asynchronous activ e-lo w input f or both po w er ing do wn the de vice and po w er ing up the de vice . when pd# is asser ted, all cloc ks will be dr iv en high, or tr i-stated (depending on the pd# dr iv e mode and output control bits) bef ore the pll is shut do wn. pd#, p o wer do wn when pd# is sampled lo w b y tw o consecutiv e r ising edges of dif#, all dif outputs m ust be held high, or tr i-stated (depending on the pd# dr iv e mode and output control bits) on the ne xt high-lo w tr ansition of the dif# outputs . when the pd# dr iv e mode bit is set to ?0?, all cloc k outputs will be held with dif dr iv en high with 2 x i ref and dif# tr i-stated. if the pd# dr iv e mode bit is set to ?1?, both dif and dif# are tr i-stated. pd# asser tion pow er-up latency is less than 1 ms . this is the time from de-asser tion of the pd# pin, or vdd reaching 3.3v , or the time from v alid src_in cloc ks until the time that stab le cloc ks are output from the de vice (pll loc k ed). if the pd# dr iv e mode bit is set to ?1?, all the dif outputs m ust dr iv en to a v oltage of >200 mv within 300 us of pd# de-asser tion. pd# de-asser tion pwrdwn# dif dif# pwrdwn# dif dif# tstable <1ms tdrive_pwrdwn# <300us, >200mv note: p olar ities in timing diag r ams are sho wn oe_inv = 0. the y are similar to oe_inv = 1.
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 15 advance information asserting dif_stop# causes all dif outputs to stop after their next transition (if the control register settings allow the outputto stop). when the dif_st op# dr iv e bit is ?0?, the final state of all stopped dif outputs is dif = high and dif# = lo w. there is no change in output dr iv e current. dif is dr iv en with 6xi ref . dif# is not dr iv en, b ut pulled lo w b y the ter mination. when the dif_st op# dr iv e bit is ?1?, the final state of all dif output pins is lo w. both dif and dif# are not dr iv en. dif_st op# - asser tion all stopped diff erential outputs resume nor mal oper ation in a glitch-free manner . the de-asser tion latency to activ e outputs is 2-6 dif cloc k per iods , with all dif outputs resuming sim ultaneously . if the dif_st op# dr iv e control bit is ?1? (tr i-state), all stopped dif outputs m ust be dr iv en high (>200 mv) within 10 ns of de-asser tion. dif_st op# - de-asser tion (transition fr om '0' to '1') the dif_stop# signal is an active-low asynchronous input that cleanly stops and starts the dif outputs. a valid clock mustbe present on dif_in f or this input to w or k proper ly . the dif_st op# signal is de-bounced and m ust remain stab le f or tw o consecutiv e r ising edges of dif# to be recogniz ed as a v alid asser tion or de-asser tion. dif_st op# dif_st op_1 (dif_stop = driven, pd = driven) dif_st op_2 (dif_stop =t ristate , pd = driven) pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms dif pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms dif
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 16 advance information dif_st op_4 (dif_stop = t ristate , pd = t ristate) dif_st op_3 (dif_stop = driven, pd = t ristate) pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms dif pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms dif
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 17 advance information 209 mil ssop min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions 209 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.65 basic 28-pin ssop package dimensions
idt tm /ics tm four output dif ferential buf fer for pcie gen 2 with s pread 1626 09/17/09 ics9ds400 four output differential buffer for pcie for gen 2 with spread 18 advance information 9ds400 ordering information part / order number marking shipping packaging package ambient operating temperature 9ds400aglf 9ds400aglf tubes 28-pin tssop 0 to +70 c 9ds400aglft 9ds400aglf tape and reel 28-pin tssop 0 to +70 c 9ds400agilf 9ds400agilf tubes 28-pin tssop -40 to +85 c 9ds400agilft 9ds400agilf tape and reel 28-pin tssop -40 to +85 c 9ds400aflf 9ds400aflf tubes 28-pin ssop 0 to +70 c 9ds400aflft 9ds400aflf tape and reel 28-pin ssop 0 to + 70 c 9DS400AFILF 9DS400AFILF tubes 28-pin ssop -40 to +85 c 9DS400AFILFt 9DS400AFILF tape and reel 28-pin ssop -40 to +85 c parts that are ordered with a ?lf? suffix to the pa rt number are the pb-free configuration and are roh s compliant. indexarea 1 2 n d e1 e a seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 de e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol 28-pin tssop p acka g e dimensions
ics9ds400 four output differential buffer for pcie gen 2 with spread 19 advance information innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and jap an integrated device t echnology singapore (1997) pte. lt d. reg. no. 199707558g 435 orchard road #20-03 w isma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett w ood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify product s or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 9/16/2009 initial release. 0.2 9/17/2009 updated idd specs in input/supply/common output par ameters table 5

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